Integrated circuits are now well known and extensively used in various technologies. Over the last decade, the operating speeds and packing densities have increased substantially while the device size has been dramatically reduced. The combination of increased packing density and device size reduction have posed ever new problems for the semiconductor fabrication industry that have not previously been of concern. One such area of fabrication involves the formation of isolation structures located on the semiconductor wafer substrate, between transistor devices, to provide electrical isolation between the devices. A variety of techniques, generally termed isolation processes, have been developed to isolate transistors in integrated circuits.
One such process is local oxidation of silicon (LOCOS), in which a silicon nitride (Si3N4) film is used to isolate selected regions of the semiconductor substrate in which field oxide structures are formed. This isolation technique has been widely used as an isolation technique of very large-scale integrated (VLSI) circuits. While this technique has been quite useful and extensively used in larger submicron devices, its use in smaller, present day submicron technologies has encountered limitations due to the increased packing density.
To overcome the limitations associated with the LOCOS process, the industry devised an alternative isolation process known as shallow trench isolation (STI). This particular process provides an isolation structure that requires less surface area on the semiconductor substrate. However, even this process has encountered limitations in view of the advent of layout schemes that include high and low component density areas.
After filling the trench with the oxide, a planarization process is conducted and the oxide is over polished to make certain that the oxide is removed everywhere on the wafer down to the underlying hardmask and that there are not any areas on the wafer that have oxide remaining on the surface of the hardmask. A draw back to this over polish step, however, is that dishing of the oxide within the trench may occur in certain areas of the wafer, which results in the hardmask being higher than the oxide. When the hardmask is removed, a corner portion of the oxide is removed to form trench encroachments on either side of the trench. These encroachments become gathering spots for polysilicon during the poly gate deposition step. This polysilicon is difficult to remove, and the polysilicon filled trench encroachment areas can produce some leakage from the sub-threshold voltage degradation that will, in turn, affect device performance.
In attempts to overcome this trench encroachment problem, some manufacturers have chosen to dramatically increase the thickness of the hardmask layer. This procedure, unfortunately, has the drawback of causing problems with the lithographic processes used to pattern the hardmask. In addition, the added thickness in the hardmask increases the aspect ratio, which makes it more difficult to fill the trench with the oxide. Another attempt to correct the trench encroachment problem has been to modify the slurry used to remove the oxide. This attempt, however, has also encountered problems in variation in pattern density in those layout schemes involving high density component areas and low density component areas.
Accordingly, what is needed in the art is a trench isolation structure that does not experience the trench encroachment experienced by the conventional methods.